Process monitor test chip and methodology
US5831446A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jul 12, 1996 |
| Grant date | Nov 3, 1998 |
| Priority date | — |
| Expiry date | Jul 12, 2016 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L22/34
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A process monitor test chip and methodology allows process-related manufacturing defects to be quickly identified and isolated. A basic circuit block of a test chip having a number of inverter cells serially connected with a corresponding number of observation points before the input of each inverter cell provides for the inverter cells in the basic circuit block to be probed and thus observed by e-beam technology. Any required number of basic circuit blocks may be serially connected end to end to constitute a chain circuit. Within the test chip itself, a plurality of chain circuits may be connected serially or in parallel to accomplish different testing goals. By controlling an input signal and a control signal of a multiplexing element associated with each chain circuit, the plurality of chain circuits can be forced into a serial connection or a parallel connection. In a serial mode, the plurality of chain circuits are serially connected with one input signal and one output signal of the test chip; the serial connection may be used during burn-in of the test chip to test for whether the test chip contains any process-related manufacturing defects. Once it has been determined that…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.