Protection method for power transistors, and corresponding circuit
US5831466A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 27, 1996 |
| Grant date | Nov 3, 1998 |
| Priority date | — |
| Expiry date | Dec 27, 2016 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K2217/0072
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
The present invention is aimed at providing a method and a circuit for protecting the output stage of a power actuator against voltage transients of the surge type. In particular, it provides protection against voltage surge transients of the kind described by International Standard IEC 801-5, for a power transistor contained in the output stage of the actuator. The method of this invention provides for: PA1 the utilization of the power transistor (PW) intrinsic diode (DP) for dumping the transient energy to one of the supply generator terminals during a positive transient; and PA1 the utilization of the power transistor (PW) restoration feature to the on state for dumping the energy thereinto during a negative transient, while simultaneously inhibiting the current limiting function. The power transistor (PW) is turned on again, and the current limiting circuit (4) inhibited, by the following steps: PA1 a) generating an electric signal which is substantially proportional to the voltage appearing at the output terminal (OUT) of the actuator; PA1 b) driving the control terminal (G) of the power transistor (PW) by means of said electric signal, and causing said transistor to conduct, …
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.