Vertical synchronizing signal stabilizing circuit, integrated circuit and television signal processing device
US5831682A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Aug 22, 1996 |
| Grant date | Nov 3, 1998 |
| Priority date | — |
| Expiry date | Aug 22, 2016 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04N5/08
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
In a vertical synchronizing signal stabilizing circuit, an integrated circuit and a television signal processing device, a vertical synchronizing signal of which period is stabilized can be output with a small number of elements and a simple constitution, without being influenced by the state of the television signal. On the basis of a first distinguish signal which indicates whether there is a separated signal separated from the television signal as the vertical synchronizing signal or not and of a second distinguish signal which indicates whether the period of the separated signal is the standard period or not, the plural states of the separated signal are discriminated, and the processing mode of the separated signal processing circuit is switched on the basis of the result of the discrimination to process the separated signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.