Method and system for characterizing interconnect data within an integrated circuit for facilitating parasitic capacitance estimation
US5831870A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 7, 1996 |
| Grant date | Nov 3, 1998 |
| Priority date | — |
| Expiry date | Oct 7, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/398
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and system for characterizing interconnect data within an integrated circuit in order to facilitate parasitic capacitance estimation is disclosed. An integrated circuit typically includes a substrate layer and several metal layers. In accordance with the method and system of the present invention, an overlapping area of interconnect wires is first identified within the integrated circuit. This overlapping area, which is a polygon, may be formed between the substrate layer and at least one interconnect wire in one of the several metal layers. The overlapping area may also be formed between two interconnect wires, each in a different one of the several metal layers. A netname for the overlapping area is then recorded. Finally, a netname of an interconnect wire in a metal layer that is at the same level of an interconnect wire within the overlapping area and an associated distance from each side of the overlapping area is recorded, for every interconnect wire within the overlapping area. By utilizing these recorded information, the parasitic capacitance of the integrated circuit can be estimated more efficiently.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.