Static random access memory semiconductor layout
US5831898A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jan 14, 1997 |
| Grant date | Nov 3, 1998 |
| Priority date | — |
| Expiry date | Jan 14, 2017 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S257/904
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A static random access memory device (SRAM) keeping a resistance value of a resistance element at a predetermined level regardless a process variation, by improving a special margin of a diffusion layer region at which the resistance element is formed and a node for connecting a gate electrode thereto. In the SRAM, there is provided a diffusion layer region in a substrate, having a first part of which may form a the resistance element, a second part of which is connected to the drain or source of the MIS access transistor, and a third part of which is connected to the source or drain of the MIS driver transistor and is defined the node, and there is provided an electrode layer connecting the gate of the MIS driver transistor and the node in the diffusion layer region. The diffusion layer region is formed so that the diffusion layer region is bent at the first part which may form the resistance element and is defined the node and a first direction between the first part and the second part and a second direction between the first part and the third part intersect at an obtuse angle.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.