Semiconductor memory having space-efficient layout
US5831912A · kind A · utility
Assignees
Inventors
Key dates
| Filing date | Sep 26, 1997 |
| Grant date | Nov 3, 1998 |
| Priority date | — |
| Expiry date | Sep 26, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/4097
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present disclosure includes semiconductor memory with a space efficient layout. Dynamic Random Access Memory (DRAM) chips have a plurality of memory cells (18) arranged in rows and columns. A semiconductor memory includes a bank of sense amplifiers (14) disposed in a first generally rectangular region having a length parallel to said rows, with each sense amplifier (14) in the bank disposed in a sense amplifier region of an associated column (16). A plurality of amplifiers (124 or 126) are driven by at least one driver (140 or 142), each of the plurality of amplifiers disposed between a pair of complementary bit lines (120) and located within the sense amplifier region. The at least one driver shares at least one diffusion region extending transversely to the column direction with at least on other driver such that the number of contacts of the sense amplifier bank is reduced.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.