Multiprocessors system for selectively wire-oring a combination of signal lines and thereafter using one line to control the running or stalling of a selected processor
US5832253A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 6, 1993 |
| Grant date | Nov 3, 1998 |
| Priority date | — |
| Expiry date | Dec 6, 2013 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F15/17325
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present invention provides for a computer system having a plurality of parallel processor units. The processor units are connected in common to a signal line with each processor capable of setting a first signal level on the line and monitoring the line in response to instructions to the processor. This allows each processor unit to be notified of the completion of a parallel operation by other participating processor units upon a second signal level on the signal line. More than one signal lines may be connected between the parallel processor units to provide synchronization of different parallel operations between different processor units.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.