Semiconductor device having an element with circuit pattern thereon
US5834844A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 22, 1996 |
| Grant date | Nov 10, 1998 |
| Priority date | — |
| Expiry date | Mar 22, 2016 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3025
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A process for making a chip sized semiconductor device, in which a semiconductor chip is prepared so as to have electrodes on one of surfaces thereof and an electrically insulating passivation film formed on the one surface except for areas where the electrodes exist. An insulation sheet is prepared so as to have first and second surfaces and a metallic film coated on the first surface. The second surface of the insulation sheet is adhered on the one surface of the semiconductor chip. First via-holes are provided in the metallic film at positions corresponding to the electrodes. Second via-holes are provided in the insulation sheet at positions corresponding to the first via-holes so that the electrodes are exposed. The metallic film is electrically connected to the electrodes of the semiconductor chip through the first and second via-holes. A circuit pattern is formed from the metallic film so that the circuit pattern has external terminal connecting portions. An insulation film is adhered on the insulation sheet so that the external terminal connecting portions are exposed. External connecting terminals are electrically connected to the external terminal connecting portions of th…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.