Analog-to-digital converter with improved cell mismatch compensation
US5835048A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Jan 22, 1997 |
| Grant date | Nov 10, 1998 |
| Priority date | — |
| Expiry date | Jan 22, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/36
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An analog-to-digital converter (ADC) formed on an integrated circuit chip from a plurality of cells includes a differential amplifier having first and second branches. The branches in each cell respectively have first and second transistors respectively responsive to an input voltage and an individual one of progressive fractions of a reference voltage. The relative outputs from the branches for each cell are dependent upon the relative values of the two voltages introduced to the cell. To minimize cell mismatches and the effects of these mismatches on cell outputs, first and second sets of averaging impedances, preferably resistors, are respectively connected between the output terminals of the first branch transistors, and between the output terminals of the second branch transistors, in successive pairs of cells. Current sources connected to the output terminals of the transistors in the first and second branches have characteristics (preferably impedances approaching infinity) to force the load bearing currents from the transistors to flow through the impedances in the first and second sets. The impedances have relatively low values, particularly in comparison to the impedances…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.