Addressable imaging
US5835246A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Mar 12, 1995 |
| Grant date | Nov 10, 1998 |
| Priority date | — |
| Expiry date | Mar 12, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06E3/005
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A means, method and apparatus for producing a parallel addressable set of images by modulating a set of input beams with addressing information, and projecting the energy from a three-dimensional array of first pixel locations which decode in parallel to produce an interference image at the location of a second three-dimensional array of pixel locations, energizing at least one of the second pixels. Each image corresponds with an input address. A subset of addresses, projection surface configurations, and images exhibit useful synergistic relationships. These are used to address a ROM, RAM, or content addressable memory, provide a visual display of selected images, iterate in a series to produce four dimensional computing, integrate information from multiple energy forms, and accomplish signal processing and channel switching.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.