Patent · US Expired

Current conductor arrangement

US5835362A · kind A · utility

5Cited by

10References

6Claims

0Family size

Assignee

Asea Brown Boveri, S.A. · CH

Inventors

Markus Keller · Leonberg, DE
Jochen Rees · Waldshut-Tiengen, DE
Alexander Stoev · Forch, CH

Key dates

Filing date	Mar 14, 1996
Grant date	Nov 10, 1998
Priority date	—
Expiry date	Mar 14, 2016

Classification

Technology area (CPC H)Electricity
CPC primaryH02M7/003
WIPO fieldElectrical machinery, apparatus, energy
WIPO sectorElectrical engineering

Abstract

In order to reduce the commutation inductance of series-connected controllable semiconductor components (V1-V6), the latter are connected, in an essentially orthogonal manner and at a predeterminable distance (a), via spur double striplines (6, 6') to essentially planar main lines (5, 5'). All of the double striplines (5, 5'; 6, 6') have a layered structure and are mutually insulated by a thin insulating layer (7), with the result that a minimum current area is achieved. The controllable semiconductor components (V1-V6) are accommodated closely adjacent to freewheeling diodes in a module (10), the heat of which can be dissipated by cooling elements (8). Bipolar transistors having an insulated gate (IGBTs) are preferably used as controllable semiconductor components (V1-V6).

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.