Power factor and crest factor circuit
US5835369A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Jul 8, 1997 |
| Grant date | Nov 10, 1998 |
| Priority date | — |
| Expiry date | Jul 8, 2017 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02B70/10
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
A power factor and crest factor correction circuit for a power distribution network of the type comprising a low power source for supplying a plurality of ports with an ac signal is disclosed. Each port comprises a rectifier bridge, a bulk storage capacitor and a power converter connected across the rectifier bridge, The power factor and crest factor correction circuit comprises an inductor, series connected between the rectifier bridge and the bulk capacitor, for reducing the current peaks in a rectified signal received from the rectifier bridge. The correction circuit also comprises diode means connected in parallel across the inductor for discharging the bulk capacitor whenever the voltage across the bulk capacitor exceeds the voltage of the rectified signal. As a result, a higher power factor is obtained for the dc signal applied to the power converter, and also the current peaks in the dc signal are substantially reduced.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.