Semiconductor memory device with clamping circuit for preventing malfunction
US5835419A · kind A · utility
11Cited by
9References
14Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 27, 1997 |
| Grant date | Nov 10, 1998 |
| Priority date | — |
| Expiry date | Feb 27, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/832
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory device includes: subarrays having memory cells each arranged at cross points of a plurality of bit lines and a plurality of word lines; a row decoder for selecting among the word lines; a column decoder for supplying a select signal to transfer gates for selecting among paired bit lines; and a clamping circuit for fixing the potential of a column select line at a constant potential before the column decoder is activated.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.