Method of providing redundancy in electrically alterable memories
US5835430A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jul 25, 1997 |
| Grant date | Nov 10, 1998 |
| Priority date | — |
| Expiry date | Jul 25, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/76
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method of providing redundancy in an electrically alterable memory divided into addressable blocks within the memory. The electrically alterable memory should have more available blocks than required by the firmware. The method includes the steps of testing the memory to create block status information about good versus bad blocks, writing the block status information into a table in the electrically alterable memory, reordering the table so that contiguous series of entries in the table point only to good blocks, and then providing a block status array comprising block select registers which are initialized with the corresponding ones of the contiguous series of entries so that a nominal address to a bad block is redirected to a good block.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.