Method and apparatus for wafer test of redundant circuitry
US5835431A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Sep 5, 1997 |
| Grant date | Nov 10, 1998 |
| Priority date | — |
| Expiry date | Sep 5, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/24
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and apparatus for testing redundant circuitry within a memory array is provided. A control unit is described to interface a memory array to a wafer tester to selectively enable redundant rows/columns within a memory array during wafer test, without requiring permanent alteration of row/column select switches. Temporary enabling of redundant rows/columns allows testing of redundancy prior to alteration of the permanent switch logic. The control unit, upon command from a wafer tester, selectively enables particular redundant rows/columns to allow those redundant rows/columns to be tested. After testing, if the redundant rows/columns repair memory defects, permanent switch logic may be altered, without requiring further testing of the redundant circuitry.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.