Hyper page mode control circuit for a semiconductor memory device
US5835449A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Nov 27, 1996 |
| Grant date | Nov 10, 1998 |
| Priority date | — |
| Expiry date | Nov 27, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/1024
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An output control circuit for a semiconductor memory device allows the output data to be controlled by a write enable line and/or an output enable line in hyper page mode. An output write enable control signal is generated in response to a column address strobe signal, an output enable signal and a write enable signal. A precharge signal is generated in response to the output write enable control signal, thereby allowing a data bus line to be precharged in hyper page mode. The output enable signal and the write enable signal can be selectively coupled to an output write enable control signal generating circuit to allow the output control circuit to operate in different modes. A trigger signal, which controls a data output buffer and driver circuit, is controlled in response to a latch signal. The latch signal is generated by latching the write enable signal in response to the column address strobe signal. The output control circuit allows the data bus line to be precharged between consecutive bits of output data in hyper page mode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.