Method for fast determination of puesdo-noise code generator state
US5835528A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Jul 8, 1997 |
| Grant date | Nov 10, 1998 |
| Priority date | — |
| Expiry date | Jul 8, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04B1/7075
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
A method for setting the state of a clock-driven pseudo-noise sequence generator ("PNSG") having N stages, after the clock has been inhibited for a predetermined number K of clock cycles, to the state S.sub.2 (D) the PNSG would have been had the clock not been inhibited, based on the state S.sub.1 (D) the PNSG is in at the time inhibition of the clock is commenced. The method involves performing the following steps. First, a previously determined value, a(D)=the remainder of D.sup.Kq /f(D), is stored, wherein D is the delay transform operator, q=2.sup.N -2, and f(D)=c.sub.1 D.sup.N +c.sub.2 D.sup.N-1 + . . . +c.sub.N D+1. The product S.sub.2 (D)=a(D)S.sub.1 (D) is formed, wherein S.sub.1 (D)=s.sub.11 D.sup.N-1 +s.sub.12 D.sup.N-2 + . . . +s.sub.1N D.sup.0. If the degree of S.sub.2 (D) does not exceed N-1, the state bit values for S.sub.2 (D) are inferred from the product. However, if the degree of S.sub.2 (D) exceeds N-1, the product S.sub.2 (D) is first reduced by f(D), and then the state bit values for S.sub.2 (D) are inferred from the product.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.