Digital desynchronizer
US5835543A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jul 16, 1997 |
| Grant date | Nov 10, 1998 |
| Priority date | — |
| Expiry date | Jul 16, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04J3/076
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
A digital desynchronizer device (10) includes an elastic store unit (12) that receives data in an asynchronous manner and synchronously transmits the data in response to a synchronization clock generated by a clock generator (14). The clock generator (14) operates off of a reference oscillator unit (16). The clock generator (14) generates the synchronization clock signal in response to pointer adjustments identified by a pointer movement unit (18). The clock generator (14) also generates the synchronization clock signal in response to mapping jitter identified by a mapping unit (20). The pointer movement unit (18) and the mapping unit (20) identify pointer adjustments and mapping jitter, respectively, independent of each other. The clock generator (14) adjusts a width of a specific pulse bit in response to pointer adjustments identified by the pointer movement unit (18). Clock generator (14) also adjusts a width of a specific bit position, separate from the pulse bit position used for pointer adjustments, in response to mapping jitter identified by the mapping unit (20).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.