System and method for executing indivisible memory operations in multiple processor computer systems with multiple busses
US5835742A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 14, 1994 |
| Grant date | Nov 10, 1998 |
| Priority date | — |
| Expiry date | Jun 14, 2014 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/30087
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus for performing indivisible memory operations on memory locations in remote memory means in multiple bus, multiple processor computer systems comprises a logic supervisor coupled to a bus bridge. The logic supervisor comprises a lock address register, a buffer address register, a command register, a first parameter register, a second parameter register, a first latch, a second latch, a comparator, and a controller. The controller is a state machine that observes instruction sequences intended to create an indivisible memory operation on a remote bus. When the logic supervisor detects an indivisible memory operation instruction sequence with a remote address, it gathers the data for the indivisible memory operation, inhibits the processor, and hands the data off to the bus bridge. When the logic supervisor receives a completion status from the bus bridge it places the returned value in memory and releases the processor. Should the logic supervisor detect an indivisible memory operation instruction sequence, but not a remote address, the logic supervisor does not participate in the indivisible memory operation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.