Method for executing different sets of instructions that cause a processor to perform different data type operations on different physical registers files that logically appear to software as a single aliased register file
US5835748A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 19, 1995 |
| Grant date | Nov 10, 1998 |
| Priority date | — |
| Expiry date | Dec 19, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3861
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and apparatus for executing different sets of instructions that cause a processor to perform different data type operations on different physical registers files that logically appear to software as a single aliased register file. According to one aspect of the invention, a processor is provided that includes at least two physical register files--one for executing scalar data type operations and the other for executing packed data type operations. In addition, the processor includes a transition unit that is configured to cause the two physical register files to logically appear to software executing on the processor as a single logical register file.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.