Packed/add and packed subtract operations
US5835782A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 4, 1996 |
| Grant date | Nov 10, 1998 |
| Priority date | — |
| Expiry date | Mar 4, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2207/3828
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A processor having a circuit for performing a packed addition and/or packed subtraction operation. The decoder accesses the registers addressed by SRC1 and SRC2. These registers provide a first packed data and a second packed data to the circuit. Packed data consists of a number of fixed length data elements. The data elements can be eight bits, sixteen bits or thirty-two bits in length. The circuit performs the operation on the first data element from the first packed data and the first data element from second packed data, producing a first result data element. The circuit performs this operation on the next data element from the first packed data and the next data element from the second packed data, producing a next result data element. This continues for all the data elements in the first and second packed data. The result data elements constitute a result packed data that is stored in the destination register.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.