Memory system with multiplexed input-output port and memory mapping capability
US5835965A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Apr 24, 1996 |
| Grant date | Nov 10, 1998 |
| Priority date | — |
| Expiry date | Apr 24, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0292
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory 600 including an array of memory cells 201 and a plurality of input/output terminals 220 for receiving control bits during control cycles and accessing selected ones of the cells 201 during data access cycles. A command bit input terminal 221 is provided for receiving command bits for initiating the control cycles and a mapping input terminal 222 is provided for receiving a mapping enable signal to initiate a mapping mode. Circuitry 215/ 216 is provided for decoding control bits received during at least one control cycle occurring during a mapping mode for allowing a mapping of a set of addresses for accessing the cells of the array 201.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.