Fabrication of zero layer mask
US5837404A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Jan 4, 1997 |
| Grant date | Nov 17, 1998 |
| Priority date | — |
| Expiry date | Jan 4, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG03F7/70433
- WIPO fieldOptics
- WIPO sectorInstruments
Abstract
A method of fabricating a universal zero layer photomask of an integrated circuit is disclosed. With this method, only one universal zero layer mask is required for all the integrated circuit products; thus, the production cost can be reduced. In this method, the alignment marks and one or more vernier patterns are located near the edge of the effective exposure field of the wafer which takes up only a very small area of the wafer. Furthermore, the zero layer layout of the product also places the alignment marks and the vernier patterns in the same corner as the photomask. During the alignment, the wafer moves back and forth in both X and Y directions so as to match the previously recorded alignment marks positions on the mask.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.