Stacked assemblies of semiconductor packages containing programmable interconnect
US5838060A · kind A · utility
Inventor
Key dates
| Filing date | Dec 12, 1995 |
| Grant date | Nov 17, 1998 |
| Priority date | — |
| Expiry date | Dec 12, 2015 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/30107
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A stackable semiconductor package is described which has external contact points (pins, pads, solder-bumps, etc.), which are arranged in arrays on the top and bottom surfaces of the package. This package also has internal contact points (bond pads) for connection to an integrated circuit die. The external and internal connection points are connected by a programmable interconnection matrix, which may be manufactured separately from the package body and then assembled within the package. The internal contact points can each be selectively connected to the external contact points, and selective connections can also be made linking pairs of the external contact points. Stacks of such packages, containing different dice, may be formed, creating large, tightly-coupled circuit blocks. A presently-preferred embodiment of the programmable package is described in which the package body and programmable matrix are manufactured as a unit. The described embodiment comprises a package body (12) with a formed recess (14) for receiving a package lid (50) surrounding a deeper die cavity (16), both on the package's top surface. After mounting, an integrated circuit die (20) is connected through int…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.