Method and apparatus for providing ESD/EOS protection for IC power supply pins
US5838146A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Nov 12, 1996 |
| Grant date | Nov 17, 1998 |
| Priority date | — |
| Expiry date | Nov 12, 2016 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH02H9/046
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
An apparatus and method for providing EOS/ESD protection against an EOS/ESD event across first and second pads of an integrated circuit. In one embodiment, the EOS/ESD protection circuit includes an NMOS device having a drain and source respectively coupled to the first and second pads of the integrated circuit, a capacitor coupled between the drain and gate of the NMOS device and a clamping circuit coupled between the gate and the source of the NMOS device to maintain a voltage at the gate less than or equal to a clamping voltage of the clamping circuit. In embodiments of the present invention, the protection circuit includes an active pull down circuit for reducing the voltage across the gate and source of the NMOS device to zero volts a predetermined period of time after the EOS/ESD event, and the protection circuit further includes a current source for providing bias current to the clamping circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.