High performance self modifying on-the-fly alterable logic FPGA, architecture and method
US5838165A · kind A · utility
Inventor
Key dates
| Filing date | Aug 21, 1996 |
| Grant date | Nov 17, 1998 |
| Priority date | — |
| Expiry date | Aug 21, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F15/7867
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A technique for configuring arrays of programmable logic cells, including those associated with FPGA devices, through a novel DRAM-based configuration control structure that enables not only "on-the-fly" alterable chip and similar device reconfigurations, but, where desired, self-modifying reconfigurations for differing functionalities of the devices, eliminating current serious reconfigurability limitations and related problems, while providing significantly enhanced system performance at low cost. A large amount of memory is available internal to the FPGA and is accessed with a small number of pins such that the reconfiguration time is, for example, four orders of magnitude faster than the traditional approaches and at notably low cost.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.