Bias circuit for switched capacitor applications
US5838191A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Feb 21, 1997 |
| Grant date | Nov 17, 1998 |
| Priority date | — |
| Expiry date | Feb 21, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04N25/773
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
An adaptive bias circuit for switched capacitor applications that compensates for temperature and process variations by maintaining a constant settling time of CMOS operational amplifiers is introduced. To this end, the adaptive bias circuit allows a dynamic trade-off between the slew-rate and the gain bandwidth product which allows the output of the operational amplifier to settle within a certain predetermined precision. A first aspect of the invention includes a current source providing a same current to a pair of transistors having different effective current densities. A resistor is coupled between the pair of transistors while from one end of the resistor, a constant bias current is drawn. In this manner, a voltage difference develops across the resistor which effectively indicates the change in the transconductance of the pair of transistors with respect to temperature and process variations. Another aspect of the invention allows the bias circuit to minimize the body effect, the back bias effect, the channel length modulation effect, as well as the dependence of circuit performance upon the power supply voltage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.