Three-transistor static storage cell
US5838606A · kind A · utility
7Cited by
20References
12Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 28, 1997 |
| Grant date | Nov 17, 1998 |
| Priority date | — |
| Expiry date | Apr 28, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/41
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A SRAM storage cell has a NMOS transistor and a PMOS transistor connected with each other between a source of potential and ground. The sources, gates and gate back plates of the transistors are commonly connected and coupled to a storage node. The drain of the NMOS transistor is supplied with the potential, whereas the drain of the PMOS transistor is grounded. A pass NMOS transistor is connected between the storage node and bit and word lines. This storage cell configuration provides considerably reduced area compared to conventional static storage cells.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.