Reading circuit for multilevel non volatile memory cell devices
US5838612A · kind A · utility
28Cited by
5References
9Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 4, 1997 |
| Grant date | Nov 17, 1998 |
| Priority date | — |
| Expiry date | Jun 4, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2211/5631
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Reading circuit for multilevel non-volatile memory cell devices having, for each cell to be read, a selection line with which is associated a load and a decoupling and control stage with a feedback loop which stabilizes the voltage on a circuit node of the selection line. To this node are connected a current replica circuit which are controlled by the feedback loop. These include loads and circuit elements homologous to those associated with the selection line of the memory cell and have an output interface circuit for connection to current comparator circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.