Bit error counting method and counting technical field
US5838697A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Apr 29, 1997 |
| Grant date | Nov 17, 1998 |
| Priority date | — |
| Expiry date | Apr 29, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/4107
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An error detecting device and method for use when applying the Viterbi decoding to an inputted signal, when it is necessary to derive the number of errors included in a decoded signal. A value of a path metric derived upon the Viterbi decoding is read out and outputted as the number of errors. Two kinds of decoding devices, each reading out a value of a path metric and outputting this value as the number of errors, are provided for a sound signal and an FACCH signal. A signal is inputted to both devices for decoding, respectively. The numbers of errors derived from both devices are compared, and it is judged based on a result of the comparison, whether the inputted signal is the sound signal or the FACCH signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.