Alignment of parity bits to eliminate errors in switching from an active to a standby processing circuit
US5838698A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Apr 28, 1995 |
| Grant date | Nov 17, 1998 |
| Priority date | — |
| Expiry date | Apr 28, 2015 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L1/22
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
Glitchless switching between active and standby telecommunication apparatus having hierarchical nested parity bits is provided. A higher order parity bit is calculated based on defined data as well as a lower order parity bit. A method is provided for aligning each parity bit generated by a standby processor with a corresponding parity bit independently generated by an active processor. This alignment is accomplished prior to output frames of data being supplied by the standby processor in order to provide glitchless switching such that the first frame of data supplied by the standby processor contains parity bits which are in agreement with the corresponding data in the frame.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.