Elastic bus interface data buffer
US5838936A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 10, 1997 |
| Grant date | Nov 17, 1998 |
| Priority date | — |
| Expiry date | Mar 10, 2017 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An elastic bus interface receives and registers an external data transfer signal and generates an internal data transfer signal that always begins at the beginning of the subsequent clock cycle regardless of the time of arrival of the external data transfer signal. By employing a plurality of data output registers in a pipeline and using only the internal data transfer signal, data is fed to a bus so as to ensure that almost a complete clock cycle is available for setup time to accomplish data transfer. The invention can operate with high speed buses using only simple conventional circuitry and modest process geometries requiring only minimal chip area and power.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.