Tunable software control of harvard architecture cache memories using prefetch instructions
US5838945A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Oct 17, 1997 |
| Grant date | Nov 17, 1998 |
| Priority date | — |
| Expiry date | Oct 17, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/6028
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Disclosed is an instruction-level method and system for prefetching data or instructions of variable size to specified cache sets. A prefetch instruction containing binary fields allows the compiler, loader or runtime software to control cache prefetching and reduce thrashing by providing the prefetch hardware with information as to the optimal cache set location and the optimal amount of data to be prefetched. Support of Harvard architectures with separate instruction and data caches is provided by separate software control of instruction and data caches. The cache set number is identified to indicate into which set the information is to be preloaded. The size field provides a variable prefetch size. An address field indicates the address where prefetching begins.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.