Controller for providing access to a video frame buffer in split-bus transaction environment
US5838955A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | May 3, 1995 |
| Grant date | Nov 17, 1998 |
| Priority date | — |
| Expiry date | May 3, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG09G2360/126
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A system includes a requesting agent coupled to a system bus. The system bus includes an address bus, control lines for indicating a requested transfer type, a data bus, address bus arbitration control lines and data bus arbitration control lines. The system further includes a system bus arbiter coupled to the system bus for resolving competing requests for access to the address bus and for separately resolving competing requests for access to the data bus. A graphics controller for enabling the requesting agent to access a frame buffer has a memory, which may be a FIFO, responsive to a first control signal, for storing data received from a frame buffer. The memory is further responsive to a second control signal for supplying the stored data to the data bus. The graphics controller also includes a controller coupled to the system bus and to the memory means. In response to a frame buffer read request from the requesting agent, the controller initiates a frame buffer read operation in accordance with parameters contained in the received frame buffer read request, and also initiates a request for access to the data bus. The first control signal is generated in response to data assoc…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.