Multi-stage timer implementation for telecommunications transmission
US5838957A · kind A · utility
24Cited by
1References
16Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 1, 1996 |
| Grant date | Nov 17, 1998 |
| Priority date | — |
| Expiry date | Feb 1, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/4825
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Telecommunications networks require a large number of timers to support the necessary dispatching of tasks. These timers require significant CPU cycles. The present invention describes a method and apparatus for reducing the CPU requirements of timers while maintaining their utility and accuracy by using multi-class periodic timers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.