Method of operation and apparatus for optimizing execution of short instruction branches
US5838961A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Oct 1, 1996 |
| Grant date | Nov 17, 1998 |
| Priority date | — |
| Expiry date | Oct 1, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3804
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A technique for speeding CPU operations in handling branch instructions in which the target instructions is a short displacement away from its branch instruction is disclosed. When the target instruction is displaced within a predetermined number of instructions away, a logic block and counter issue an invalidating control signal which invalidates the execution of the branch instruction and instructions between the branch instruction and the target instruction. The invalidating control signal is removed when the target instruction is reached. Time is saved if the latency of the computer system is longer than the time required to cycle the instruction queue to the target instruction.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.