Processor for eliminating external isochronous subsystems
US5838987A · kind A · utility
15Cited by
15References
18Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 6, 1995 |
| Grant date | Nov 17, 1998 |
| Priority date | — |
| Expiry date | Oct 6, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2209/542
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A processing system having a virtual subsystem architecture employs a reentrant system management mode mechanism and device handlers along with remappable hardware resources to simulate physical subsystems, all transparent to application programs executing on the processing system.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.