Method for reducing via inductance in an electronic assembly and article
US5841075A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Jan 28, 1998 |
| Grant date | Nov 24, 1998 |
| Priority date | — |
| Expiry date | Jan 28, 2018 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10T29/49165
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of making a low inductance conductive via in a laminated substrate by providing a first conductive layer. A first dielectric layer is formed on the first conductive layer. A second conductive layer is formed on the first dielectric layer. A first conductive path is formed in the first conductive layer extending along a first route between a first node and a second node. A first conductive blind-via is connected to the first conductive path at the second node, with the first-blind via being formed in the first dielectric layer at the second node. Lastly, a second conductive path is formed in the second conductive layer that is connected to the first blind via. The second conductive path extends between a third node and the first blind via along a second route. The second route corresponds identically to at least a portion of the first route.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.