Power-down circuit
US5841269A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Aug 1, 1997 |
| Grant date | Nov 24, 1998 |
| Priority date | — |
| Expiry date | Aug 1, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F1/305
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A power-down circuit includes a power-on reset circuit that determines whether the supplied power falls below a prescribed level and, in response, outputs a reset signal for at least a prescribed period of time. A power supply latching circuit is responsive to the power-on reset circuit for switching on a power supply switching circuit to supply power from a power supply when the reset signal is not output. A power-down shutdown circuit, preferably under software control, and a power cutoff circuit, may be coupled to the power supply latching circuit, or alternatively the power-on reset circuit, for shutting down the power supplied from the power supply.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.