High performance programmable interconnect
US5841694A · kind A · utility
22Cited by
10References
28Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jul 30, 1997 |
| Grant date | Nov 24, 1998 |
| Priority date | — |
| Expiry date | Jul 30, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/17792
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A high performance programmable interconnect enables scaled transistors to be utilized, in conjunction with memory cells, as transfer gates with improved speed characteristics. Boosted positive and negative drive voltages are supplied to the transfer gate depending on the programmed state of the memory cell. The transfer gate may be driven by an inverter using a transistor formed in a triple well.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.