Semiconductor memory device with redundancy switching method
US5841711A · kind A · utility
26Cited by
3References
6Claims
0Family size
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Key dates
| Filing date | Aug 28, 1997 |
| Grant date | Nov 24, 1998 |
| Priority date | — |
| Expiry date | Aug 28, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory device with a redundancy switching system is operable in first and second modes. In the first mode, data read from a memory element is compared with external data, and if the compared data do not agree with each other, an external address is latched. In the second mode, the latched external address is written into a redundancy switching nonvolatile memory element. The first and second modes are selected with the same signal for each memory chip.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.