Methods for backplane interconnect testing
US5841788A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Oct 18, 1996 |
| Grant date | Nov 24, 1998 |
| Priority date | — |
| Expiry date | Oct 18, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/2815
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A backplane testing method is provided in which test vectors are applied to individual circuit boards in a system while remaining circuit boards in the system are disabled. The signals on all receivers in the system are observed during testing. The circuit boards are connected to a test bus in a multi-drop arrangement, so that individual circuit boards can be addressed using slave interfaces. A walking enable technique is used to systematically toggle all of the drivers on the circuit boards. An intraboard testing technique is used for applying test vectors including an all 0's vector, an all 1's vector, and a series of test vectors generated from a binary counting sequence. Backplane faults are identified by comparing the observed receiver signals to the signals expected in response to the applied test vectors.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.