Counter circuit with multiple registers for seamless signal switching
US5842006A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Sep 6, 1995 |
| Grant date | Nov 24, 1998 |
| Priority date | — |
| Expiry date | Sep 6, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F7/68
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A counter circuit with multiple registers for eliminating reprogramming delays and for providing seamless switching between timing signals. In a first embodiment, two registers are preloaded with values and control logic chooses between the registers for loading a counter. The counter asserts a terminal count signal to output logic, which correspondingly asserts a convert pulse to an analog measuring circuit. The control logic receives start and stop signals and the terminal count signal, where the control logic controls operation accordingly. In this manner, a delay value is initially loaded into the counter to provide an initial delay period upon receiving the start signal, and then a scan rate value is continually loaded into the counter from another register thereafter for defining the scan rate until the start signal is received. Alternatively, first and second scan rate values are preloaded into the first and second registers, respectively, and a select signal is used as a gate signal to identify which of the scan rates to use. In this manner, the scan rate is almost immediately switched to the new rate when the gate signal is toggled to achieve seamless switching. In an alte…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.