Method and apparatus for implementing a branch target buffer cache with multiple BTB banks
US5842008A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 18, 1996 |
| Grant date | Nov 24, 1998 |
| Priority date | — |
| Expiry date | Jun 18, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3806
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A Branch Target Buffer Circuit in a computer processor that predicts branch instructions within a stream of computer instructions is disclosed. The Branch Target Buffer Circuit uses a Branch Target Buffer Cache with multiple BTB banks that store branch information about previously executed branch instructions. The branch information stored in each bank of the Branch Target Buffer Cache is addressed by the last byte of each branch instruction When an Instruction Fetch Unit in the computer processor fetches a block of instructions it sends the Branch Target Buffer Circuit an instruction pointer. Based on the instruction pointer, the Branch Target Buffer Circuit looks in the Branch Target Buffer Cache banks to see if any of the instructions in the block being fetched is a branch instruction. When the Branch Target Buffer Circuit finds an upcoming branch instruction in the Branch Target Buffer Cache, the Branch Target Buffer Circuit informs an instruction Fetch Unit about the upcoming branch instruction.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.