CMOS tristate output buffer with having overvoltage protection and increased stability against bus voltage variations
US5844425A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jul 19, 1996 |
| Grant date | Dec 1, 1998 |
| Priority date | — |
| Expiry date | Jul 19, 2016 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/00315
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An overvoltage tolerant CMOS tristate output buffer capable of withstanding tristate overvoltages without reverse currents or latch-up, the output buffer having a stabilized protection circuit for driving the N-well and gate of the P-channel driver transistor to the output pad voltage when the output pad voltage becomes excessive. The stabilized protection circuit includes a hysteresis circuit for controlling switch transistors which bias the N-well. The presence of the hysteresis circuit causes the protection circuit to have an input hysteresis characteristic, thus preventing excessive switching of the N-well biasing transistors when the output pad voltage varies near the output buffer power supply voltage during tristate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.