Low noise low power CMOS correlated double sampler
US5844431A · kind A · utility
56Cited by
6References
9Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Sep 18, 1996 |
| Grant date | Dec 1, 1998 |
| Priority date | — |
| Expiry date | Sep 18, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C27/026
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An improved CMOS CDS circuit which can operate on 2.7 volts, provides increased noise immunity and can handle a 0.8 volts maximum signal input. The present invention provides internal capacitors to isolate the input pads. The present invention also provides switches and capacitors to perform a sample and hold function on every pixel value.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.