Method of recovering a sampling clock in a framed data communications format with reduced phase jitter and wander
US5844436A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Nov 6, 1996 |
| Grant date | Dec 1, 1998 |
| Priority date | — |
| Expiry date | Nov 6, 2016 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/0337
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
To reduce drift in a sampling clock for framed data, a phase detector senses the time difference between (i) the time when a reference mark for the framed data is received and (ii) the time when the nominal number of oversampling clock cycles between reference timing marks is received. This difference is output to a clock controller which chooses a phase change rate based thereon. This phase change rate is applied to an oversampling clock to continuously, progressively, change the phase of the oversampling clock in a sense which tends to reduce this phase error. The phase changing clock is divided down by a frequency divider to generate a sampling clock. The phase of the oversampling clock is changed by generating multiple, equally spaced, phases of the oversampling clock and progressively changing the selection of the active phase.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.