Differential flipflop circuit operating with a low voltage
US5844437A · kind A · utility
39Cited by
3References
10Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 28, 1997 |
| Grant date | Dec 1, 1998 |
| Priority date | — |
| Expiry date | Mar 28, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K3/289
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
In a flipflop circuit, each of master and slave latch/hold circuits is constituted of differential pairs consisting of transistors each connected between VCC and VSS without being in series with another transistor between VCC and VSS. A clock driving circuit has a pull-down function responding to a pair of complementary clocks so as to pull down the level of a pair of complementary data signals supplied to each latch/hold circuit. With this arrangement, the flipflop circuit composed of bipolar transistors can operate with a low voltage of not greater than 1 V.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.