Method for creating and using design shells for integrated circuit designs
US5844818A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | May 10, 1996 |
| Grant date | Dec 1, 1998 |
| Priority date | — |
| Expiry date | May 10, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/33
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for creating a shell to represent a functional block of an IC design comprising of a plurality of interconnected functional blocks. The critical information from a synthesized gate level block is retained in the shell such that when analyzing the static characteristics of another block connected to the block now represented by the shell the analysis is still accurate. At a hierarchial level the present invention provides a method for analyzing the functional blocks of an IC design such that the memory requirement for storing the information of the functional blocks of the IC design is reduced as well as a decrease in run time.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.