Row address control circuits having a predecoding address sampling pulse generator and methods for memory devices
US5844857A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Sep 19, 1997 |
| Grant date | Dec 1, 1998 |
| Priority date | — |
| Expiry date | Sep 19, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C8/06
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A row address control circuit for a memory device includes a row address enable signal generator, a row address buffer, a row predecoder, a row address strobe buffer, a predecoded row address sampling pulse generator, and a row decoder. The row address enable signal generator produces a row address enable signal which is enabled while a clock signal is enabled. The row address buffer receives the output of the row address enable signal generator and produces a row address signal enabled while the row address enable signal is enabled. The row predecoder receives and predecodes the output of the row address buffer and produces a predecoded row address signal. The row address strobe buffer receives the clock signal and produces a first control signal while the clock signal is enabled. The predecoded row address sampling pulse generator receives the output of the row address strobe buffer and produces a predecoded row address sampling pulse signal for selecting the predecoded row address signal while the first control signal is enabled. The row decoder receives the output of the predecoded row address sampling pulse generator and the row predecoder and has its output connected to a wor…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.